Sr. ASIC/FPGA Verification Engineer (UVM)

Location: San Jose, CA
Category: Engineering
Employment Type: Contract
Job ID: 31525
08/06/2021

Our client in the networking space is looking for an engineer to report into the ASIC/FPGA team as a key member. This engineer will own the Whole Process & Methodology for UVM wireless network (this includes wi-fi).

Job Description:
– Verify designs and implementation of the industry's leading network monitoring devices.
– Develop and integrate current and future RTL designs into a UVM (DV) environment.
– Create reports providing coverage and testing results to the teams to help troubleshoot issues in the design.
– Role may also require creating behavioral models of designs, and developing RTL, which will be integrated into the testing environment.
– Own the Whole Process & Methodology for UVM wireless network (includes wi-fi).

– Verify designs and implementation of the industry's leading network monitoring devices.

– Verification of FPGA and/or ASIC designs, architecture, golden models, and micro-architecture; using advanced verification methodologies, in particular, UVM.

– Own pre-silicon verification, post-silicon validation, and system bring-up; all the way to production.

– Develop and integrate current and future designs into UVM environments.

– Design and implementation, define verification scopes, develop verification infrastructure, and verify the correctness of designs.

– Document and execute test plans on various platforms for DUT (design under test).

– Specify, develop, and debug constrained random verification test suites to fully verify DUT.

– Generate reports providing coverage and test results.

– Integrate Verification into continuous integration flow, and into CI tools like TeamCity.

– Work with architects, designers, software and hardware teams, execs, in various locations, to accomplish tasks.

– Report into the ASIC/FPGA team as a key member.

 

Required/Desired:

– UVM verification of network devices – Required Experience.

  • Includes constrained-random packet generation, non- cycle accurate transaction-level models and scoreboards.

– Design and verification tools exp.

– DV exp. required, (vs RTL Design exp.).

– Crafting test bench environments for unit and system level verification.

– System Verilog.

– Strong debugging, troubleshooting and analytical skills.

– Understand design and implementation, verification scopes, how to develop verification infrastructure and verify the correctness of designs.

– Python programming language experience desirable.

– Networking and packet processing is a plus.

– Strong communication skills and ability & desire to work as a great teammate.

– Technically curious and driven to learn new skills.

– Self-starter, flexible, adaptable, collaborative, and motivated to champion continuous improvement.

– Must be able to work independently under basic management direction.

– Master’s Degree in EE, CS, or CE; with at least 5+ years of relevant experience.

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