COVID-19 Response

Sr. ASIC/FPGA Verification Engineer (UVM)

Office: San Mateo | Date Added: April 28, 2021 | Job ID: 31525

Our client in the networking space is looking for an engineer to report into the ASIC/FPGA team as a key member. This engineer will own the Whole Process & Methodology for UVM wireless network (this includes wi-fi).

Job Description:

– Verify designs and implementation of the industry's leading network monitoring devices.

– Verification of FPGA and/or ASIC designs, architecture, golden models, and micro-architecture; using advanced verification methodologies, in particular, UVM.

– Integrate Verification into continuous integration flow, and into CI tools like TeamCity.


Desired:

– UVM verification of network devices.

  • Includes constrained-random packet generation, non- cycle accurate transaction-level models and scoreboards.

– Design and verification tools exp.

– Crafting test bench environments for unit and system level verification.

– System Verilog.

– Strong debugging, troubleshooting and analytical skills.

– Understand design and implementation, verification scopes, how to develop verification infrastructure and verify the correctness of designs.

– Python programming language experience desirable.
 

Mainz Brady Group is a technology staffing firm with offices in California, Oregon and Washington. We specialize in Information Technology and Engineering placements on a Contract, Contract-to-hire and Direct Hire basis. Mainz Brady Group is the recipient of multiple annual Excellence Awards from the Techserve Alliance, the leading association for IT and engineering staffing firms in the U.S.

Mainz Brady Group is an Equal Opportunity Employer. We are committed to Diversity & Inclusion and incorporate non-discrimination best practices in all of our staffing processes. Mainz Brady Group does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, gender expression, age, disability or any other protected class.

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